HD64F2636F20 Datasheet, PDF (619/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Bit 5
IRTR
0
1
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
• When 0 is written in IRTR after reading IRTR = 1
• When the IRIC flag is cleared to 0
Continuous transfer state
[Setting conditions]
• In I²C bus interface slave mode
When the TDRE or RDRF flag is set to 1 when AASX = 1
• In other modes
When the TDRE or RDRF flag is set to 1
(Initial value)
Bit 4—Second Slave Address Recognition Flag (AASX): In I²C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
0
1
Description
Second slave address not recognized
[Clearing conditions]
(Initial value)
• When 0 is written in AASX after reading AASX = 1
• When a start condition is detected
• In master mode
Second slave address recognized
[Setting condition]
• When the second slave address is detected in slave receive mode and FSX = 0
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 569 of 1458