HD64F2636F20 Datasheet, PDF (1215/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
MBCR0—Mailbox Configuration Register
MBCR1—Mailbox Configuration Register
H'F804
H'FA04
HCAN0
HCAN1^*
Bit
15
14
13
12
11
10
9
8
MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 ⎯
Initial value
0
0
0
0
0
0
0
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit
7
6
5
4
3
2
1
0
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
Mailbox Setting Register
0 Corresponding mailbox is set for transmission
1 Corresponding mailbox is set for reception
Note: * This register is not available in the H8S/2635 Group.
TXPR0—Transmit Wait Register
TXPR1—Transmit Wait Register
H'F806
H'FA06
HCAN0
HCAN1^*
Bit
15
14
13
12
11
10
9
8
TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 ⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
TXPR8
0
R/W
Transmit Wait Register
0 Transmit message idle state in corresponding mailbox
[Clearing condition]
• Message transmission completion and cancellation completion
1 Transmit message transmit wait in corresponding mailbox
(CAN bus arbitration)
Note: * This register is not available in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1165 of 1458