HD64F2636F20 Datasheet, PDF (225/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 7 Bus Controller
16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
φ
Address bus
AS
RD
Read D15 to D8
Valid
D7 to D0
HWR
Write
LWR
D15 to D8
D7 to D0
Invalid
High
Valid
High impedance
Figure 7-10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 175 of 1458