HD64F2636F20 Datasheet, PDF (1368/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
LPWRCR—Low-Power Control Register
H'FDEC
System
Bit
7
6
5
4
3
2
DTON*¹ LSON*¹ NESEL*¹ SUBSTP*¹ RFCUT*¹ ⎯
Initial value
0
0
0
0
0
0
Read/Write R/W
R/W R/W
R/W
R/W R/W
1
STC1
0
R/W
0
STC0
0
R/W
Frequency Multiplication Factor
0 0 ×1
1 ×2
1 0 ×4
1 Setting prohibited
Oscillation Circuit Feedback Resistance Control Bit
0 When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF
1 Sets the feedback resistance OFF
Subclock Enable
0 Enables subclock generation
1 Disables subclock generation
Noise Elimination Sampling Frequency Select
0 Sampling using 1/32 × φ
1 Sampling using 1/4 × φ
Low-Speed ON Flag
0 • When the SLEEP instruction is executed in high-speed mode or medium-speed mode,
operation shifts to sleep mode, software standby mode, or watch mode*
• When the SLEEP instruction is executed in sub-active mode, operation shifts to watch
mode or shifts directly to high-speed mode
• Operation shifts to high-speed mode when watch mode is cancelled
1 • When the SLEEP instruction is executed in high-speed mode, operation shifts to watch
mode or sub-active mode
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode or watch mode
• Operation shifts to sub-active mode when watch mode is cancelled
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Direct Transition ON Flag
0 • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
to sleep mode, software standby mode, or watch mode*
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or
watch mode
1 • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
directly to sub-active mode*, or shifts to sleep mode or software standby mode
• When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed
mode, or shifts to sub-sleep mode
Note: _* Always set high-speed mode when shifting to watch mode or sub-active mode.
Note: 1. Bits 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are
reserved bits in all other versions.
See sections 23A.2.3, 23B.2.3, Low-Power Control Register (LPWRCR), for more information.
Page 1318 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010