HD64F2636F20 Datasheet, PDF (1092/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 24 Electrical Characteristics
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
(4) Timing of On-Chip Supporting Modules
Table 24-42 lists the timing of on-chip supporting modules.
Table 24-42 Timing of On-Chip Supporting Modules
Conditions: V_CC = 4.5 V to 5.5 V, PWMV_CC = 4.5 V to 5.5 V, AV_CC = 4.5 V to 5.5 V,
V_ref = 4.5 V to AV_CC, V_SS = PWMV_SS = PLLV_SS = AV_SS = 0 V,
T_a = –20°C to +75°C (regular specifications), T_a = –40°C to +85°C (wide-range
specifications)
Item
Symbol
I/O port
PPG
TPU
PWM
SCI
Output data delay time
tPWD
Output data delay time 2
tPWD2
Input data setup time
tPRS
Input data hold time
tPRH
Pulse output delay time
tPOD
Timer output delay time
tTOCD
Timer input setup time
tTICS
Timer clock input setup time tTCKS
Timer clock Single edge
pulse width _{Both edges}
tTCKWH
tTCKWL
Pulse output delay time
tMPWMOD
Input clock
cycle
Asynchronous tScyc
Synchronous
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
tSCKW
tSCKr
tSCKf
tTXD
tRXS
Receive data hold time
tRXH
(synchronous)
A/D
Trigger input setup time
converter
tTRGS
Condition
Min. Max.
—
50
—
50
30
—
30
—
—
50
—
50
30
—
30
—
1.5
—
2.5
—
—
50
4
—
6
—
0.4
0.6
—
1.5
—
1.5
—
50
50
—
50
—
50
—
Unit Test Conditions
ns
Figure 24-18
Figure 24-19
ns
Figure 24-20
ns
Figure 24-21
ns
Figure 24-22
tcyc
ns
Figure 24-23
tcyc
Figure 24-24
tScyc
tcyc
ns
Figure 24-25
ns
Figure 24-26
Page 1042 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010