HD64F2636F20 Datasheet, PDF (241/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 8 Data Transfer Controller (DTC)
8.1.3 Register Configuration
Table 8-1 summarizes the DTC registers.
Table 8-1 DTC Registers
Name
DTC mode register A
DTC mode register B
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Abbreviation
MRA
MRB
SAR
DAR
CRA
CRB
R/W
—^*2
—^*2
—^*2
—^*2
—^*2
—^*2
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Address^*1
—^*3
—^*3
—^*3
—^*3
—^*3
—^*3
DTC enable registers
DTCER
R/W H'00
H'FE16 to H'FE1C
DTC vector register
DTVECR
R/W H'00
H'FE1F
Module stop control register A
MSTPCRA R/W H'3F
H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, do not clear the RAME
bit in SYSCR to 0.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 191 of 1458