HD64F2636F20 Datasheet, PDF (1387/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
TMDR3—Timer Mode Register 3
H'FE81
TPU3
Bit
7
⎯
Initial value
1
Read/Write
⎯
6
5
4
3
2
1
0
⎯
BFB BFA MD3 MD2 MD1 MD0
1
0
0
0
0
0
0
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Mode
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
1*** ⎯
*: Don't care
Notes: 1. MD3 is a reserved bit. In a write,
it should always be written with 0.
2. Phase counting mode cannot be
set for channel 3. In this case, 0
should always be written to MD2.
Buffer Operation A
0 TGRA operates normally
1 TGRA and TGRC used together for buffer operation
Buffer Operation
0 TGRB operates normally
1 TGRB and TGRD used together for buffer operation
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1337 of 1458