HD64F2636F20 Datasheet, PDF (702/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
Hardware reset
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)^*1
GSR3 = 1 (automatic)
Initialization of HCAN module
Clear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method initialization
MCR0 = 0
GSR3 = 0?
No
Yes
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
GSR3 = 0 &
No
11 recessive bits received?
Yes
CAN bus communication enabled
: Settings by user
: Processing by hardware
Notes: 1.
2.
When IRR0 is set to 1 (automatically) due to a hardware reset^*2, a "hardware reset
initiated reset processing" interrupt is generated.
In a reset and in hardware standby mode, the module stop bit is initialized to 1
and the HCAN enters the module stop state.
Figure 16-4 Hardware Reset Flowchart
Page 652 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010