HD64F2636F20 Datasheet, PDF (1462/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TCSR1—Timer Control/Status Register 1
H'FFA2(W), H'FFA2(R)
Bit
Initial value
Read/Write
7
OVF
0
R/(W)^*1
6
WT/IT
0
R/W
5
TME
0
R/W
4
3
2
PSS^*2 RST/NMI CKS2
0
0
0
R/W R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
WDT1
Clock Select 2 to 0
PSS CKS2 CKS1 CKS0 Clock
0
0
0
0 φ/2
1 φ/64
1
0 φ/128
1 φ/512
1
0
0 φ/2048
1 φ/8192
1
0 φ/32768
0
1
1
1 φ/131072
1
0
0
0 φSUB/2*2
1 φSUB/4*2
1
0 φSUB/8*2
1 φSUB/16*2
1
0
0 φSUB/32*2
1 φSUB/64*2
1
0 φSUB/128*2
1 φSUB/256*2
Overflow Period*1 (where φ = 20 MHz)
(where φSUB*2 = 32.768 kHz)
25.6 μs
819.2 μs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1s
2s
Notes: 1.
2.
Reset or NMI
An overflow period is the time interval between the start of counting up
from H'00 on the TCNT and the occurrence of a TCNT overflow.
Subclock functions (subactive mode, subsleep mode, and watch mode)
are available in the U-mask, W-mask versions, and H8S/2635 Group
only, but are not available in the other versions.
0 NMI request
1 Internal reset request
Prescaler Select
0 The TCNT counts frequency-division clock pulses of the φ based prescaler (PSM)
1 The TCNT counts frequency-division clock pulses of the φ SUB*-based prescaler (PSS)
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask, W-mask versions, and H8S/2635 Group only. These functions cannot be used with
the other versions, and in them the PSS bit is reserved. Only 0 should be written to this bit.
Timer Enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows
1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows
Overflow Flag
0 [Clearing conditions]
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR* when OVF = 1, then write 0 in OVF
1 _{[Setting condition]}
• When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset)
Note: * When interval timer interrupts are disabled and OVF is polled, read the OVF = 1 state at least twice.
Notes: TCSR1 register differs from other registers in being more difficult to write to. For details see section 12.2.4, Notes on Register Access.
1. Only 0 can be written, to clear the flag.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask, W-mask versions, and
H8S/2635 Group only.
Page 1412 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010