HD64F2636F20 Datasheet, PDF (475/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
Section 12 Watchdog Timer
12.1 Overview
The chip has two channel inbuilt watchdog timers (WDT0/WDT1). The WDT can also generate
an internal reset signal for the chip if a system crash prevents the CPU from writing to the timer
counter, allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• An internal reset can be issued if the timer counter overflows
⎯ In the watchdog timer mode, the WDT can generate an internal reset
• Interrupt generation when in interval timer mode
⎯ If the counter overflows, the WDT generates an interval timer interrupt
• WDT0 and WDT1 respectively allow eight and sixteen types*¹ of counter input clock to be
selected
⎯ The maximum interval of the WDT is given as a system clock cycle × 131072 × 256
⎯ A subclock*² may be selected for the input counter of WDT1
⎯ Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 ×
256
Notes: 1. Other than the U-mask and W-mask versions, and H8S/2635 Group have eight types of
counter input clock as well as WDT0.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in
the U-mask and W-mask versions, and H8S/2635 Group only.
See section 22A.7, Subclock Oscillator, for the method of fixing pins when OSC1 and
OSC2 are not used. The H8S/2639 and H8S/2635 Groups have no OSC1 and OSC2
pins.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 425 of 1458