HD64F2636F20 Datasheet, PDF (684/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been
reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after
reset input or recovery from software standby mode, interrupt handling will be performed as soon
as interrupts are enabled by the interrupt controller.
Bit 8: IRR0
Description
0
[Clearing condition]
• Writing 1
1
Hardware reset (HCAN module stop^*, software standby)
(Initial value)
[Setting condition]
• When reset processing is completed after a hardware reset (HCAN
module stop^*, software standby)
Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the
HCAN enters the module stop state.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.
Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in HCAN sleep mode.
Bit 4: IRR12
0
1
Description
CAN bus idle state
[Clearing condition]
(Initial value)
• Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
• Bus operation (dominant bit detection) in HCAN sleep mode
Page 634 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010