HD64F2636F20 Datasheet, PDF (180/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
16 Bit Bus
Symbol
Internal 2-State
Memory Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch
SI 1
4
6 + 2m
2
Branch address read
SJ
Stack manipulation
SK
Legend:
m: Number of wait states in an external device access.
3+m
5.5 Usage Notes
5.5.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5-8 shows an example in which the TCIEV bit in the TPU’s TIER register is cleared to 0.
Page 130 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010