HD64F2636F20 Datasheet, PDF (494/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
12.5.2 Changing Value of PSS* and CKS2 to CKS0
If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before changing the value of bits PSS* and CKS2 to CKS0.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4 Internal Reset in Watchdog Timer Mode
The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, but TCNT and TSCR of the WDT are reset.
12.5.5 OVF Flag Clearing in Interval Timer Mode
If conflict occurs between OVF flag clearing and OVF flag reading in interval timer mode, the
flag may not be cleared by writing 0 to OVF even though the OVF = 1 state has been read. When
interval timer interrupts are disabled and the OVF flag is polled, for instance, and there is a
possibility of conflict between OVF flag setting and reading, the OVF = 1 state should be read at
least twice before writing 0 to OVF in order to clear the flag.
Page 444 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010