HD64F2636F20 Datasheet, PDF (1369/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
BARA—Break Address Register A
BARB—Break Address Register B
H'FE00
H'FE04
PBC
PBC
Bit
31 ^{. . .} 24 23 22 21 20 19 18 17 16 ^{. . .} 7 6 5 4 3 2 1 0
⎯ ^{. . .} ⎯ ^{BAA BAA BAA BAA BAA BAA BAA BAA . . . BAA BAA BAA BAA BAA BAA BAA BAA}
23 22 21 20 19 18 17 16
7 6 543 2 10
Initial value _Unde- . . . _{Unde- 0 0 0 0 0 0 0 0} . . . _{0 0 0 0 0 0 0 0}
fined
fined
Read/Write ⎯ ^{. . .} ⎯ R/W R/W R/W R/W R/W R/W R/W R/W ^{. . .} R/W R/W R/W R/W R/W R/W R/W R/W
Break Address 23 to 0
Specify the channel A or B break address
Notes: 1. The bit configuration of BARB is the same as for BARA.
2. These registers are not available in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1319 of 1458