HD64F2636F20 Datasheet, PDF (388/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
10.2.5 Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:
7
6
5
4
3
2
1
0
—
—
—
TCFV TGFD TGFC TGFB TGFA
Initial value :
1
1
0
0
0
0
0
0
R/W
:—
—
—
R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Can only be written with 0 for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:
Initial value :
R/W
:
7
TCFD
1
R
6
5
4
3
—
TCFU TCFV
—
1
0
0
0
—
R/(W)^* R/(W)^*
—
Note: * Can only be written with 0 for flag clearing.
2
1
0
—
TGFB TGFA
0
0
0
—
R/(W)^* R/(W)^*
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
Page 338 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010