HD64F2636F20 Datasheet, PDF (634/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Master receive mode
Set TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
Clear IRIC flag in ICCR
Set WAIT = 1 (ICMR)
Read ICDR
[1] Set to receive mode
[2] Receive start, dummy read
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Set ACKB = 1 (ICSR)
Set TRS = 1 (ICCR)
Clear IRIC flag in ICCR
[3] Receive wait state (IRIC set at falling edge
of 8th clock cycle) or
Wait for end of reception of 1 byte
(IRIC set at rising edge of 9th clock cycle)
[7] Set acknowledge data for final receive
[9] Set TRS to generate stop condition
[11] Clear IRIC flag (cancel wait state)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Set WAIT = 0 (ICMR)
Clear IRIC flag in ICCR
Read ICDR
Write BBSY = 0
and SCP = 0 (ICCR)
End
[12] Wait for end of reception of 1 byte
(IRIC set at rising edge of 9th clock cycle)
[15] Cancel wait mode
Clear IRIC flag (IRIC flag should be
cleared when WAIT = 0)
[16] Read final receive data
[17] Generate stop condition
Figure 15-11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
(Example)
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 15-11 for details.
Page 584 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010