HD64F2636F20 Datasheet, PDF (456/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Programmable Pulse Generator (PPG)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Address H'FE2D
Bit
:
Initial value :
R/W
:
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Address H'FE2F
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value :
1
1
1
1
1
1
1
1
R/W
:—
—
—
—
—
—
—
—
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and
the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4
of address H'FE2E are reserved bits that cannot be modified and are always read as 1.
Address H'FE2C
Bit
:
7
6
5
4
3
2
1
0
NDR15 NDR14 NDR13 NDR12 —
—
—
—
Initial value :
0
0
0
0
1
1
1
1
R/W
: R/W
R/W
R/W
R/W
—
—
—
—
Address H'FE2E
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— NDR11 NDR10 NDR9 NDR8
Initial value :
1
1
1
1
0
0
0
0
R/W
:—
—
—
—
R/W
R/W
R/W
R/W
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is
H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that
cannot be modified and are always read as 1. However, the chip has no output pins corresponding
to pulse output groups 0 and 1.
Page 406 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010