HD64F2636F20 Datasheet, PDF (1438/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
ICCR0—I²C Bus Control Register
ICCR1—I²C Bus Control Register
H'FF78
H'FF80
IIC0
IIC1
Bit
:7
ICE
Initial value : 0
R/W
: R/W
6
5
4
3
2
1
0
IEIC MST TRS ACKE BBSY IRIC SCP
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/(W)* R/W
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition,
in combination with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
I²C Bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress
1 Interrupt requested
Note: * For details see section 15.2.5, I²C Bus
Control Register.
Bus busy
0 Bus is free
[Clearing condition]
• When a stop condition is detected
1 Bus is free
[Clearing condition]
• When a stop condition is detected
Acknowledge bit judgement selection
0 The value of the acknowledge bit is ignored, and
continuous transfer is performed
1 If the acknowledge bit is 1, continuous transfer is
interrupted
Master/slave select, transmit/receive select
0
0 Slave receive mode
1 Slave transmit mode
1
0 Master receive mode
1 Master transmit mode
Note: * For details see section 15.2.5, I²C Bus
Control Register.
I²C Bus Interface Interrupt Enable
0 Interrupts disabled
1 Interrupts enabled
I²C Bus Interface Enable
0 I²C bus interface module disabled, with SCL and SDA signal pins set to port function
I²C bus interface module internal states initialized SAR and SARX can be accessed
1 I²C bus interface module enabled for transfer operations (pins SCL and SCA are driving
the bus)
ICMR and ICDR can be accessed
Notes: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I²C bus
interface option added.
* Only 0 can be written, for flag clearing.
Page 1388 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010