HD64F2636F20 Datasheet, PDF (240/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller
DTC
Internal address bus
On-chip
RAM
Interrupt
request
CPU interrupt
request
Internal data bus
Legend:
MRA, MRB:
DTC mode registers A and B
CRA, CRB:
DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERG: DTC enable registers A to G
DTVECR:
DTC vector register
Figure 8-1 Block Diagram of DTC
Page 190 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010