HD64F2636F20 Datasheet, PDF (794/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
Table 21A-1 Register Configuration
Register Name
Abbreviation
Mode control register
MDCR
Note: * Lower 16 bits of the address.
R/W
R/W
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Initial Value
Undefined
Address^*
H'FDE7
21A.2 Register Descriptions
21A.2.1 Mode Control Register (MDCR)
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— MDS2 MDS1 MDS0
Initial value: 1
0
0
0
0
—^*
—^*
—^*
R/W: R/W
—
—
—
—
R
R
R
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit register used to monitor the current H8S/2636 Group operating mode.
Bit 7—Reserved: Only 1 should be written to these bits.
Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be modified.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to
MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0)
input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.
21A.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0).
These settings are shown in table 21A-2.
Page 744 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010