HD64F2636F20 Datasheet, PDF (233/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 7 Bus Controller
(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
φ
Address bus
CS* (area A)
CS* (area B)
RD
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS* (area A)
CS* (area B)
RD
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Note: * The CS signal is generated externally rather than inside the LSI device.
Figure 7-16 Example of Idle Cycle Operation (2)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 183 of 1458