HD64F2636F20 Datasheet, PDF (251/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 8 Data Transfer Controller (DTC)
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8-2 outlines the functions of the DTC.
Table 8-2 DTC Functions
Address Registers
Transfer Mode
Activation Source
Transfer Transfer
Source Destination
• Normal mode
• IRQ
24 bits
24 bits
⎯ One transfer request transfers one
byte or one word
⎯ Memory addresses are incremented
or decremented by 1 or 2
⎯ Up to 65,536 transfers possible
• Repeat mode
⎯ One transfer request transfers one
byte or one word
⎯ Memory addresses are incremented
or decremented by 1 or 2
• TPU TGI
• SCI TXI or RXI
• A/D converter ADI
• Motor control PWM
CMI
• HCAN RM0
(mail box 0)
• Software
⎯ After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
• Block transfer mode
⎯ One transfer request transfers a block
of the specified size
⎯ Block size is from 1 to 256 bytes or
words
⎯ Up to 65,536 transfers possible
⎯ A block area can be designated at
either the source or destination
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 201 of 1458