HD64F2636F20 Datasheet, PDF (159/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 5 Interrupt Controller
5.2.2 Interrupt Priority Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM)
Bit
:
7
⎯
Initial value :
0
R/W
:⎯
6
5
4
3
IPR6 IPR5 IPR4
⎯
1
1
1
0
R/W R/W R/W
⎯
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5-3 Correspondence between Interrupt Sources and IPR Settings
Bits
Register
6 to 4
2 to 0
IPRA
IRQ0
IRQ1
IPRB
IRQ2
IRQ4
IPRC
IPRD
IPRE
IRQ3
—^*1
Watchdog timer 0
PC break^*3
IRQ5
DTC^*3
—^*1
A/D converter, watchdog timer 1
IPRF
TPU channel 0
TPU channel 1
IPRG
TPU channel 2
TPU channel 3
IPRH
IPRJ
TPU channel 4
—^*1
TPU channel 5
SCI channel 0
IPRK
IPRL
SCI channel 1
—^*1
SCI channel 2
IIC (Option)^*2
IPRM
PWM channel 1, 2
HCAN channel 1^*3
HCAN channel 0
Notes: 1. Reserved. These bits are always read as 1 and cannot be modified.
2. I²C bus interface is available as an option in the H8S/2638, H8S/2639, and H8S/2630.
The IIC bit becomes reserved bit when this optional feature is not used.
3. The PC break, DTC, and HCAN channel 1 are reserved in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 109 of 1458