HD64F2636F20 Datasheet, PDF (597/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
φ
PS
SCL
Noise
canceler
SDA
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address
comparator
SAR, SARX
Legend:
ICCR: I²C bus control register
ICMR: I²C bus mode register
ICSR: I²C bus status register
ICDR: I²C bus data register
SAR: Slave address register
SARX: Second slave address register X
PS: Prescaler
Interrupt
generator
Figure 15-1 Block Diagram of I²C Bus Interface
Interrupt
request
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 547 of 1458