HD64F2636F20 Datasheet, PDF (13/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
16.2.6 Transmit Wait
Cancel Register
(TXCR)
Page
626
16.2.7 Transmit
627
Acknowledge Register
(TXACK)
16.2.8 Abort
628
Acknowledge Register
(ABACK)
16.2.16 Unread
641
Message Status
Register (UMSR)
16.2.17 Local
643
Acceptance Filter
Masks (LAFML,
LAFMH)
LAFMH Bits 7 to 0 and
15 to 13
LAFMH Bits 9 and 8,
LAFML Bits 15 to 0
16.2.20 Module Stop 650
Control Register C
(MSTPCRC)
Revision (See Manual for Details)
Table amended
Bit y: TXCRx
0
1
Description
Transmit message cancellation idle state in corresponding mailbox
(Initial value)
[Clearing condition]
• Completion of TXPR clearing (when transmit message is canceled
normally)
TXPR cleared for corresponding mailbox (transmit message cancellation)
(x = 15 to 1, y = 15 to 9 and 7 to 0)
Table amended
Bit y: TXACKx
0
1
Description
[Clearing condition]
• Writing 1
(Initial value)
Completion of message transmission for corresponding mailbox
(x = 15 to 1, y = 15 to 9 and 7 to 0)
Table amended
Bit y: ABACKx
0
1
Description
[Clearing condition]
• Writing 1
(Initial value)
Completion of transmit message cancellation for corresponding mailbox
(x = 15 to 1, y = 15 to 9 and 7 to 0)
Table amended
Bit x: UMSRx
0
1
Description
[Clearing condition]
• Writing 1
Unread receive message is overwritten by a new message
(Initial value)
[Setting condition]
• When a new message is received before RXPR is cleared
(x = 15 to 0)
Table amended
Bit x: LAFMHx
0
1
Description
Stored in MC0 and MD0 (receive-only mailbox) depending on bit match
between MC0 message identifier and receive message identifier
(Initial value)
Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match
between MC0 message identifier and receive message identifier
(x = 15 to 5)
Table amended
Bit y: LAFMHx
LAFMLy
0
1
Description
Stored in MC0 (receive-only mailbox) depending on bit match between MC0
message identifier and receive message identifier
(Initial value)
Stored in MC0 (receive-only mailbox) regardless of bit match between MC0
message identifier and receive message identifier
(x = 1 and 0, y = 15 to 0)
Note amended
Note: * The MSTPC2 is not available and is reserved in the
H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page xiii of l