HD64F2636F20 Datasheet, PDF (1406/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
IPRA—Interrupt Priority Register A
H'FEC0
INT
IPRB—Interrupt Priority Register B
H'FEC1
INT
IPRC—Interrupt Priority Register C
H'FEC2
INT
IPRD—Interrupt Priority Register D
H'FEC3
INT
IPRE—Interrupt Priority Register E
H'FEC4
INT
IPRF—Interrupt Priority Register F
H'FEC5
INT
IPRG—Interrupt Priority Register G
H'FEC6
INT
IPRH—Interrupt Priority Register H
H'FEC7
INT
IPRJ—Interrupt Priority Register J
H'FEC9
INT
IPRK—Interrupt Priority Register K
H'FECA
INT
IPRL—Interrupt Priority Register L
H'FECB
INT
IPRM—Interrupt Priority Register M
H'FECC
INT
Bit
7
6
5
4
3
2
1
0
⎯
IPR6 IPR5 IPR4
⎯
IPR2 IPR1 IPR0
Initial value
0
1
1
1
0
1
1
1
Read/Write
⎯
R/W R/W R/W
⎯
R/W
R/W
R/W
Correspondence between Interrupt Sources and IPR Settings
Register
Bits
6 to 4
2 to 0
IPRA IRQ0
IRQ1
IPRB IRQ2
IRQ4
IRQ3
IRQ5
IPRC ⎯*¹
DTC*³
IPRD Watchdog timer 0
⎯*¹
IPRE PC break*³
A/D converter, watchdog timer 1
IPRF TPU channel 0
TPU channel 1
IPRG TPU channel 2
TPU channel 3
IPRH TPU channel 4
TPU channel 5
IPRJ ⎯*¹
SCI channel 0
IPRK SCI channel 1
SCI channel 2
IPRL ⎯*¹
IIC (Option)*²
IPRM PWM channel 1, 2,
HCAN channel 0
HCAN channel 1*³
Notes: 1. Reserved. Read-only bits, always read as 1.
2. I²C bus interface is available as an option in the H8S/2638, H8S/2639, H8S/2630.
The IIC bit becomes reserved bit when this optional feature is
not used.
3. The DTC, PC break, and HCAN1 are not implemented in the H8S/2635 Group.
Page 1356 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010