HD64F2636F20 Datasheet, PDF (26/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
A.1 Instruction List
Table A-1 Instruction
Set
(2) Arithmetic
Instructions
Page
1065
Revision (See Manual for Details)
Table amended
MULXU
Mnemonic
MULXU.B Rs,Rd
MULXU.W Rs,ERd
No. of States^*1
Advanced
12
20
MULXS MULXS.B Rs,Rd
13
MULXS.W Rs,ERd
21
(6) Branch Instructions 1078 Table amended
Addressing Mode/
Instruction Length (Bytes)
Mnemonic
Bcc
BVS d:8
⎯
BVS d:16
⎯
BPL d:8
⎯
BPL d:16
⎯
(7) System Control
Instructions
1080 Table amended
Operation
Branching
Condition
2
if condition is true then V=1
4
PC←PC+d
2
else next;
N=0
4
TRAPA
Mnemonic
TRAPA #xx:2
RTE
RTE
No. of States^*1
Advanced
8 [9]
5 [9]
A.4 Number of States 1109
Required for Instruction
Execution
Table A-5 Number of
Cycles in Instruction
Execution
Table amended
JMP
JMP @ERn
JMP @aa:24
JMP @@aa:8
Branch
Byte Word
Instruction Address Stack
Data Data Internal
Fetch
Read
Operation Access Access Operation
I
J
K
L
M
N
2
2
1
2
2
1
Page xxvi of l
REJ09B0103-0800 Rev. 8.00
May 28, 2010