HD64F2636F20 Datasheet, PDF (1010/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 4—Prescaler Select (PSS): This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. The operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register
(TCSR), and this section.
Bit 4
PSS Description
0
• TCNT counts the divided clock from the φ -based prescaler (PSM).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode. (Initial value)
1
• TCNT counts the divided clock from the φsubclock-based prescaler (PSS).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode^{*1 *2}, or subactive mode^{*1 *2}.
• When the SLEEP instruction is executed in subactive mode^*2, operation shifts to
subsleep mode^*2, watch mode^*2, or high-speed mode.
Notes: 1. Always set high-speed mode when shifting to watch mode or subactive mode.
2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and
H8S/2635 Group. In versions other than the U-mask and W-mask versions, and
H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock
functions are available.
Page 960 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010