HD64F2636F20 Datasheet, PDF (1009/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the
internal feedback resistance of the main clock oscillation circuit ON/OFF.
Bit 3
RFCUT Description
0
When the main clock is oscillating, sets the feedback resistance ON. When the main
clock is stopped, sets the feedback resistance OFF.
(Initial value)
1
Sets the feedback resistance OFF.
Bit 2—Reserved: Only write 0 to this bit.
23B.2.4 Timer Control/Status Register (TCSR)
Bit
:
7
6
5
4
3
2
1
0
OVF WT/IT TME PSS^*2 RST/NMI CKS2 CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/(W)^*1 R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. Only write 0 to clear the flag.
2. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and
H8S/2635 Group. In versions other than the U-mask and W-mask versions, and
H8S/2635 Group, however, the PSS bit must always be written with 0 since no subclock
functions are available.
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer
Control/Status Register (TCSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 959 of 1458