HD64F2636F20 Datasheet, PDF (956/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequency multiplication factor of the PLL circuit.
Bit 1
Bit 0
STC1
STC0
Description
0
0
×1
(Initial value)
1
×2
1
0
×4
1
Setting prohibited
Note:
The multiplication factor should be set so that the clock frequency following multiplication
does not exceed the maximum operating frequency of the LSI. It is possible to reduce
power consumption and noise by using a setting of PLL ×4 for this function and lowering the
external clock frequency.
22A.3 Oscillator
Clock pulses may be supplied either by connecting a crystal oscillator or inputting an external
clock. In the latter case, the input clock frequency should be between 4 MHz and 20 MHz.
22A.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
22A-2. Select the damping resistance R_d according to table 22A-2. An AT-cut parallel-resonance
crystal should be used.
C_L1
EXTAL
XTAL
R_d
C_L2
C_L1 = C_L2 = 10 to 22pF
Figure 22A-2 Connection of Crystal Resonator (Example)
Table 22A-2 Damping Resistance Value
Frequency (MHz)
Rd (Ω)
4
8
12
16
20
500
200
0
0
0
Page 906 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010