HD64F2636F20 Datasheet, PDF (617/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.2.6 I²C Bus Status Register (ICSR)
Bit
:
Initial value :
R/W
:
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
0
ACKB
0
R/W
Note: * Only 0 can be written, for flag clearing.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
detected during frame transfer in I²C bus format slave mode.
Bit 7
ESTP
0
1
Description
No error stop condition
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag is cleared to 0
In I²C bus format slave mode
Error stop condition detected
[Setting condition]
• When a stop condition is detected during frame transfer
In other modes
No meaning
(Initial value)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 567 of 1458