HD64F2636F20 Datasheet, PDF (1008/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing
the SLEEP instruction, this bit specifies the operating mode, in combination with other control
bits. This bit also controls whether to shift to high-speed mode or subactive mode when watch
mode is cancelled.
Bit 6
LSON Description
0
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, software standby mode, or watch mode^*.
• When the SLEEP instruction is executed in subactive mode, operation shifts to watch
mode or shifts directly to high-speed mode.
• Operation shifts to high-speed mode when watch mode is cancelled. (Initial value)
1
• When the SLEEP instruction is executed in high-speed mode, operation shifts to
watch mode or subactive mode.
• When the SLEEP instruction is executed in subactive mode, operation shifts to
subsleep mode or watch mode.
• Operation shifts to subactive mode when watch mode is cancelled.
Note: * Always set high-speed mode when shifting to watch mode or subactive mode.
Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling
frequency of the subclock (φSUB) generated by the subclock oscillator is sampled by the clock (φ)
generated by the system clock oscillator. Set this bit to 0 when φ=5MHz or more. This setting is
disabled in subactive mode, subsleep mode, and watch mode.
Bit 5
NESEL Description
0
Sampling using 1/32 × φ
1
Sampling using 1/4 × φ
(Initial value)
Bit 4—Subclock Enable (SUBSTP): This bit enables/disables subclock generation.
Bit 4
SUBSTP Description
0
Enables subclock generation
1
Disables subclock generation
(Initial value)
Page 958 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010