HD64F2636F20 Datasheet, PDF (765/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Figure 19-2 shows a block diagram of PWM channel 2.
Section 19 Motor Control PWM Timer
Interrupt
request
φ, φ/2, φ/4, φ/8, φ/16
PWCR2
Compare match
Internal
data bus
12 9
0
PWBFR2A
PWBFR2B
PWBFR2C
PWBFR2D
PWCNT2
PWOCR2
PWCYR2
9
0
PWDTR2A
PWPR2
P/N
PWDTR2B
P/N
PWDTR2C
P/N
PWDTR2D
P/N
PWDTR2E
P/N
PWDTR2F
P/N
PWDTR2G
P/N
PWDTR2H
P/N
Port
control
PWM2A
PWM2B
PWM2C
PWM2D
PWM2E
PWM2F
PWM2G
PWM2H
Legend:
PWCR2:
PWOCR2:
PWPR2:
PWCNT2:
PWCYR2:
PWDTR2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H:
PWBFR2A, 2B, 2C, 2D:
PWM control register 2
PWM output control register 2
PWM polarity register 2
PWM counter 2
PWM cycle register 2
PWM duty registers 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H
PWM buffer registers 2A, 2B, 2C, 2D
Figure 19-2 Block Diagram of PWM Channel 2
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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