HD64F3687GHV Datasheet, PDF (98/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Address Break
4.1 Register Descriptions
Address break has the following registers.
• Address break control register (ABRKCR)
• Address break status register (ABRKSR)
• Break address register (BARH, BARL)
• Break data register (BDRH, BDRL)
4.1.1 Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Initial
Bit
Bit Name Value R/W Description
7
RTINTE 1
R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
CSEL1 0
R/W Condition Select 1 and 0
5
CSEL0 0
R/W These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
Rev. 3.00 Sep. 10, 2007 Page 64 of 528
REJ09B0216-0300