HD64F3687GHV Datasheet, PDF (85/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.2.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables, timer B1 overflow interrupts.
Initial
Bit
Bit Name Value
7, 6 
All 0
5
IENTB1 0
4 to 0 
All 1
R/W

R/W

Description
Reserved
These bits are always read as 0.
Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
requests are enabled.
Reserved
These bits are always read as 1.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0
interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7
IRRDT 0
R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
Rev. 3.00 Sep. 10, 2007 Page 51 of 528
REJ09B0216-0300