HD64F3687GHV Datasheet, PDF (231/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer V
12.6 Usage Notes
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
12.12 shows the timing.
3. If compare matches A and B occur simultaneously, any conflict between the output selections
for compare match A and compare match B is resolved by the following priority: toggle output
> output 1 > output 0.
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown in
figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is seen
as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch
between internal and external clocks.
TCNTV write cycle by CPU
T₁
T₂
T₃
φ
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 12.11 Contention between TCNTV Write and Clear
Rev. 3.00 Sep. 10, 2007 Page 197 of 528
REJ09B0216-0300