HD64F3687GHV Datasheet, PDF (307/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T₂ state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 13.58 shows the timing in this case.
φ
Address bus
WGR
(internal write signal)
Input capture
signal
TCNT
GR write cycle
T1
T2
GR address
N
GR
M
GR write data
Figure 13.58 Contention between GR Write and Input Capture
8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or
vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode
after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
Rev. 3.00 Sep. 10, 2007 Page 273 of 528
REJ09B0216-0300