HD64F3687GHV Datasheet, PDF (409/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 A/D Converter
Table 18.3 A/D Conversion Time (Single Mode)
Item
Symbol Min.
A/D conversion start delay time t
6
D
Input sampling time
t
—
SPL
A/D conversion time
t
CONV
131
Note: All values represent the number of states.
CKS = 0
Typ. Max.
—
9
31
—
—
134
Min.
4
—
69
CKS = 1
Typ. Max.
—
5
15 —
—
70
18.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is
set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 18.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 18.3 External Trigger Input Timing
Rev. 3.00 Sep. 10, 2007 Page 375 of 528
REJ09B0216-0300