HD64F3687GHV Datasheet, PDF (89/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. However,
for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer
to section 19, Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits.
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address, the data in that address is sent to
the program counter (PC) as the start address, and program execution starts from that address.
The reset exception handling vector address is H'0000 to H'0001 for normal mode operation
and H'000000 to H'000003 in advanced mode operation.
Rev. 3.00 Sep. 10, 2007 Page 55 of 528
REJ09B0216-0300