HD64F3687GHV Datasheet, PDF (105/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Clock Pulse Generator
Section 5 Clock Pulse Generator
The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock
generating circuitry, and two prescalers. The system clock generating circuitry includes an
external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a
clock select circuit, and a system clock divider. The subclock generating circuitry includes a
subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry
itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock
pulse generator.
OSC1
OSC2
External
clock
φ_OSC
Duty
correction
φ_OSC
φ
oscillator
circuit
φ/8
Clock _φ System _φ/16
R_OSC
On-chip ^ROSC RC clock ^ROSC/2 ^φRC
select
circuit
clock
divider ^φ/32
φ/64
oscillator
divider _ROSC/4
System clock generating circuitry
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
X₁
Subclock
φ_W
X₂
oscillator
(f_W)
Subclock generating circuitry
Subclock
divider
φ_W/2
φ_W/4
φ_W/8
φ_SUB
Prescaler W
(5 bits)
φ_W/8
to
φ_W/128
Figure 5.1 Block Diagram of Clock Pulse Generator
The system clock (φ) and subclock (φ_SUB) are basic clocks on which the CPU and on-chip
peripheral modules operate. The system clock is divided into from φ/2 to φ/8192 by prescaler S.
The subclock is divided into from φ_W/8 to φ_W/128 by prescaler W. These divided clocks are
supplied to respective peripheral modules.
CPG0200A_000020020200
Rev. 3.00 Sep. 10, 2007 Page 71 of 528
REJ09B0216-0300