HD64F3687GHV Datasheet, PDF (370/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
Initial
Bit
Bit Name Value R/W Description
4
SDAOP 1
R/W SDAO Write Protect
This bit controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level, clear
SDAO and SDAOP to 0 or set SDAO to 1 and clear
SDAOP to 0 by the MOV instruction. This bit is always
read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL
pin outputs high. When SCLO is 0, SCL pin outputs low.
2

1

Reserved
This bit is always read as 1, and cannot be modified.
1
IICRST 0
R/W IIC Control Part Reset
This bit resets the control part except for I²C registers. If
this bit is set to 1 when hang-up occurs because of
communication failure during I²C operation, I²C control
part can be reset without setting ports and initializing
registers.
0

1

Reserved
This bit is always read as 1, and cannot be modified.
17.3.3 I²C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Initial
Bit
Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
Rev. 3.00 Sep. 10, 2007 Page 336 of 528
REJ09B0216-0300