HD64F3687GHV Datasheet, PDF (93/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Normal mode operation
Section 3 Exception Handling
SP - 4
SP - 3
SP - 2
SP - 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR*
PCH
PCL
Even address
Prior to start of interrupt
exception handling
Advanced mode operation
PC and CCR
saved to stack
After completion of interrupt
exception handling
SP - 4
SP - 3
SP - 2
SP - 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
PCE
PCH
PCL
Even address
Prior to start of interrupt
exception handling
[Legend]
PCE: Bits 23 to 16 of program counter (PC)
PC and CCR
saved to stack
After completion of interrupt
exception handling
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine.
2. Register contents must always be saved and restored in word units, starting from an even-numbered address.
* Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling
Rev. 3.00 Sep. 10, 2007 Page 59 of 528
REJ09B0216-0300