HD64F3687GHV Datasheet, PDF (305/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the
T₁ state of a GR read cycle, the data that is read will be transferred before input capture
transfer. Figure 13.56 shows the timing in this case.
GR read cycle
T1
T2
φ
GR address
Internal read
signal
Input capture
signal
GR
X
M
Internal data
bus
X
Figure 13.56 Contention between GR Read and Input Capture
Rev. 3.00 Sep. 10, 2007 Page 271 of 528
REJ09B0216-0300