HD64F3687GHV Datasheet, PDF (364/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
SCL
SDA
Output
control
Noise canceler
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
Bus state
decision circuit
Arbitration
decision circuit
ICIER
ICSR
[Legend]
ICCR1: I²C bus control register 1
ICCR2: I²C bus control register 2
ICMR: I²C bus mode register
ICSR: I²C bus status register
ICIER: I²C bus interrupt enable register
ICDRT: I²C bus transmit data register
ICDRR: I²C bus receive data register
ICDRS: I²C bus shift register
SAR: Slave address register
Interrupt
generator
Figure 17.1 Block Diagram of I²C Bus Interface 2
Interrupt request
Rev. 3.00 Sep. 10, 2007 Page 330 of 528
REJ09B0216-0300