HD64F3687GHV Datasheet, PDF (32/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
System Clock Frequencies for which Automatic Adjustment of LSI Bit
Rate is Possible ..................................................................................................... 120
Reprogram Data Computation Table .................................................................... 123
Additional-Program Data Computation Table ...................................................... 123
Programming Time ............................................................................................... 123
Flash Memory Operating States............................................................................ 128
Section 10 Realtime Clock (RTC)
Table 10.1 Pin Configuration.................................................................................................. 168
Table 10.2 Interrupt Sources................................................................................................... 178
Section 11 Timer B1
Table 11.1 Pin Configuration.................................................................................................. 180
Table 11.2 Timer B1 Operating Modes .................................................................................. 183
Section 12 Timer V
Table 12.1 Pin Configuration.................................................................................................. 187
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 189
Section 13 Timer Z
Table 13.1 Timer Z Functions ................................................................................................ 200
Table 13.2 Pin Configuration.................................................................................................. 204
Table 13.3 Initial Output Level of FTIOB0 Pin...................................................................... 235
Table 13.4 Output Pins in Reset Synchronous PWM Mode ................................................... 240
Table 13.5 Register Settings in Reset Synchronous PWM Mode........................................... 240
Table 13.6 Output Pins in Complementary PWM Mode........................................................ 244
Table 13.7 Register Settings in Complementary PWM Mode................................................ 244
Table 13.8 Register Combinations in Buffer Operation ......................................................... 254
Section 15 14-Bit PWM
Table 15.1 Pin Configuration.................................................................................................. 282
Section 16 Serial Communication Interface 3 (SCI3)
Table 16.1 Channel Configuration.......................................................................................... 286
Table 16.2 Pin Configuration.................................................................................................. 288
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 297
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 298
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 299
Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 300
Table 16.5 Examples of BRR Settings for Various Bit Rates
(Clock Synchronous Mode) (1) ............................................................................ 301
Table 16.5 Examples of BRR Settings for Various Bit Rates
(Clock Synchronous Mode) (2) ............................................................................ 302
Rev. 3.00 Sep. 10, 2007 Page xxx of xxxii