HD64F3687GHV Datasheet, PDF (119/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Clock Pulse Generator
φOSC
External clock halt
φRC
φ
OSCHLT
PHISTOP
(Internal signal)
CKSTA
CKSWIF
External clock operation
φ_OSC halt
detected*¹
φ halt*²
On-chip oscillator
clock operation
T_chk
[Legend]
φOSC: External clock
φRC:
On-chip oscillator clock
φ:
System clock
OSCHLT: Bit 1 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
Notes: 1. 44 × φ_RC ≤ T_chk ≤ 48 × φ_RC
2. The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ_RC clock.
Figure 5.8 External Oscillation Backup Timing
Rev. 3.00 Sep. 10, 2007 Page 85 of 528
REJ09B0216-0300