HD64F3687GHV Datasheet, PDF (28/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 314
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 315
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and
Receive Operations (Clock Synchronous Mode) .................................................. 317
Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor
Format (Transmission of Data H'AA to Receiving Station A)............................. 319
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 320
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 322
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 323
Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 324
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 327
Section 17 I²C Bus Interface 2 (IIC2)
Figure 17.1 Block Diagram of I²C Bus Interface 2..................................................................... 330
Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 331
Figure 17.3 I²C Bus Formats ...................................................................................................... 345
Figure 17.4 I²C Bus Timing........................................................................................................ 345
Figure 17.5 Master Transmit Mode Operation Timing (1) ......................................................... 347
Figure 17.6 Master Transmit Mode Operation Timing (2) ......................................................... 347
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 349
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 350
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 351
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 352
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 353
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 353
Figure 17.13 Clock Synchronous Serial Transfer Format .......................................................... 354
Figure 17.14 Transmit Mode Operation Timing......................................................................... 355
Figure 17.15 Receive Mode Operation Timing .......................................................................... 356
Figure 17.16 Block Diagram of Noise Filter .............................................................................. 357
Figure 17.17 Sample Flowchart for Master Transmit Mode....................................................... 358
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 359
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 360
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 361
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 363
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 368
Figure 18.2 A/D Conversion Timing .......................................................................................... 374
Figure 18.3 External Trigger Input Timing ................................................................................ 375
Figure 18.4 A/D Conversion Accuracy Definitions (1) .............................................................. 377
Rev. 3.00 Sep. 10, 2007 Page xxvi of xxxii