HD64F3687GHV Datasheet, PDF (360/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 Serial Communication Interface 3 (SCI3)
16.8 Usage Notes
16.8.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
16.8.2 Mark State and Break Sending
When the TXD or TXD2 bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction
(input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin
to mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both PCR and PDR to 1, and then set the
TXD bit to 1. At this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin.
To send a break during serial transmission, first set PCR to 1 and clear PDR to 0, and then set the
TXD bit to 1. At this point, the TxD pin becomes an I/O port regardless of the current
transmission state, and 0 is output from the TxD pin.
16.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 3.00 Sep. 10, 2007 Page 326 of 528
REJ09B0216-0300