HD64F3687GHV Datasheet, PDF(66/566 Page) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD64F3687GHV Datasheet, PDF (66/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

◁

Section 2 CPU

Table 2.11 Absolute Address Access Ranges

Absolute Address

8 bits (@aa:8)

16 bits (@aa:16)

Normal Mode

H'FF00 to H'FFFF

H'0000 to H'FFFF

24 bits (@aa:24)

H'0000 to H'FFFF

Advanced Mode

H'FFFF00 to H'FFFFFF

H'000000 to H'007FFF

H'FF8000 to H'FFFFFF

H'000000 to H'FFFFFF

(6) Immediateï£§#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

(7) Program-Counter Relativeï£§@(d:8, PC) or @(d:16, PC)

This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the

instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is â126 to +128 bytes (â63 to +64 words) or â32766 to +32768

bytes (â16383 to +16384 words) from the branch instruction. The resulting value should be an

even number.

(8) Memory Indirectï£§@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit

absolute address specifying a memory operand. This memory operand contains a branch address.

The memory operand is accessed by longword access. The first byte of the memory operand is

ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in

memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the

address range is 0 to 255 (H'0000 to H'00FF).

Note that the first part of the address range is also the exception vector area.

Rev. 3.00 Sep. 10, 2007 Page 32 of 528

REJ09B0216-0300

▷