HD64F3687GHV Datasheet, PDF (266/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
2. Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
φ
Input capture input
Input capture signal
TCNT
GR
N
N
Figure 13.18 Input Capture Signal Timing
Rev. 3.00 Sep. 10, 2007 Page 232 of 528
REJ09B0216-0300